A Hardware Acceleration Platform for Digital Holographic Imaging
Journal of VLSI Signal Processing Systems (2008)
Institution: Lund University, Sweden
Research Area: Digital holographic technology
Conclusions: This paper presents a hardware acceleration platform for image reconstruction in digital holographic imaging. The hardware accelerator executes a computationally demanding reconstruction algorithm that transforms an interference pattern captured on a digital image sensor into visible images. The focus of this work is to maximize computational efficiency and to minimize the external memory transfer overhead, as well as required internal buffering. The custom hardware accelerator, extended with a microprocessor and a memory controller, has been implemented on a custom-designed FPGA platform and integrated into a holographic microscope to reconstruct images. The proposed architecture targeting a 0.13 µm CMOS standard cell library achieves real-time image reconstruction with 20 frames per second.